RESUMEN
Ultrasound (US) neuromodulation and ultrasonic power transfer to implanted devices demand novel ultrasound transmitters capable of steering focused ultrasound waves in 3D with high spatial resolution and US pressure, while having a miniaturized form factor. Meeting these requirements needs a 2D array of ultrasound transducers directly integrated with a high-frequency 2D phased-array ASIC. However, this imposes severe challenges on the design of the ASIC. In order to avoid the generation of grating lobes, the elements in the 2D phased-array should have a pitch of half of the ultrasound wavelength, which, as frequency increases, highly reduces the area available for the design of high-voltage beamforming channels. This article addresses these challenges by presenting the system-level optimization and implementation of a high-frequency 2D phased-array ASIC. The system-level study focuses on the optimization of the US transmitter toward high-frequency operation while minimizing power consumption. This study resulted in the implementation of two ASICs in TSMC 180 nm BCD technology: firstly, an individual beamforming channel was designed to demonstrate the tradeoffs between frequency, driving voltage, and beamforming capabilities. Finally, a 12-MHz pitch matched 12 × 12 phased-array ASIC working at 20-V amplitude and 3-bit phasing was designed and experimentally validated, to demonstrate high-frequency phased-array operation. The measurement results verify the phasing functionality of the ASIC with a maximum DNL of 0.35 LSB. The CMOS chip consumes 130 mW and 26.6 mW average power during the continuous pulsing and delivering 200-pulse bursts with a PRF of 1 kHz, respectively.
